module LoadStall(
    input EX_MemR, 
    input [4:0] EX_rt, 
    input [4:0] EX_rs, 
    input [4:0] rt,
    input [4:0] rs, 
    output reg PCWr, 
    output reg IFID_Wr, 
    output reg MemW_out, 
    output reg RegW_out
);

always @(EX_MemR, EX_rt, EX_rs, rt, rt) begin
    if (EX_MemR && ((EX_rt == rs) || (EX_rt == rt)))
    begin
        PCWr = 0;
        IFID_Wr = 0;
        MemW_out = 0;
        RegW_out = 0;
    end
    else
    begin
        PCWr = 1;
        IFID_Wr = 1;
    end
end

endmodule